VND5E008ASP-E Datasheet, PDF (16/33 Pages) STMicroelectronics – Double channel high-side driver with analog current sense for automotive applications

Electrical specifications
VND5E008ASP-E
ISO 7637-2:
2004(E)
Test Pulse
Table 12. Electrical transient requirements (part 1/3)
Test levels⁽¹⁾
III
IV
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
1
-75 V
-100 V
5000
pulses
0.5 s
5s
2 ms, 10 Ω
2a
+37 V
+50 V
5000
pulses
0.2 s
5s
50 μs, 2 Ω
3a
-100 V
-150 V
1h
90 ms
100 ms 0.1 μs, 50 Ω
3b
+75 V
+100 V
1h
90 ms
100 ms 0.1 μs, 50 Ω
4
5b⁽²⁾
-6 V
+65 V
-7 V
+87 V
1 pulse
1 pulse
100 ms, 0.01 Ω
400 ms, 2 Ω
1. The above test levels must be considered referred to V_CC = 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy
allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy
along the time and to transfer a part of it to the load.
ISO 7637-2:
2004(E)
Test Pulse
Table 13. Electrical transient requirements (part 2/3)
Test level results⁽¹⁾
III
IV
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b⁽²⁾⁽³⁾
C
C
1. The above test levels must be considered referred to V_CC = 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy
allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy
along the time and to transfer a part of it to the load.
3. Suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in
Table 3: Absolute maximum ratings.
Class
C
E
Table 14. Electrical transient requirements (part 3/3)
Contents
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure
to disturbance and cannot be returned to proper operation without replacing the
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