STCF05 Datasheet, PDF (16/33 Pages) STMicroelectronics – High power white LED driver with I²C interface

I²C bus interface
Figure 5. Timing diagram on I²C bus
STCF05
8.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock
pulse. The data on the SDA line must remain stable during the HIGH period of the clock
pulse. Any change in the SDA line at this time will be interpreted as a control signal.
Figure 6. Bit transfer
8.4
16/33
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 7). The peripheral (STCF05) that acknowledges has to
pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during this clock pulse. The peripheral which has been addressed has to
generate an acknowledge pulse after the reception of each byte, otherwise the SDA line
remains at the HIGH level during the ninth clock pulse duration. In this case, the master
transmitter can generate the STOP information in order to abort the transfer. The STCF05
won't generate the acknowledge if the V_I supply is below the undervoltage lockout threshold.
Doc ID 15257 Rev 4