STA014 Datasheet, PDF (16/45 Pages) STMicroelectronics – MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM AND SRS WOWO POSTPROCESSING CAPABILITY

STA014-STA014B-STA014T
6.1 - STA014 REGISTERS DESCRIPTION
The STA014 device includes 256 I²C registers. In
this document, only the user-oriented registers
are described. The undocumented registers are
reserved. These registers must never be ac-
cessed (in Read or in Write mode). The Read-
Only registers must never be written.
The following table describes the meaning of the
abbreviations used in the I²C registers descrip-
tion:
Symbol
NA
UND
NC
RO
WO
R/W
R/WS
Comment
Not Applicable
Undefined
No Charge
Read Only
Write Only
Read and Write
Read, Write in specific mode
VERSION
Address: 0x00 (00)
Type: RO
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
V8 V7 V6 V5 V4 V3 V2 V1
The VERSION register is read-only and it is used
to identify the IC on the application board.
IDENT
Address: 0x01 (01)
Type: RO
Software Reset: 0xAC
Hardware Reset: 0xAC
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
1
0
1
0
1
1
0
0
IDENT is a read-only register and is used to iden-
tify the IC on an application board. IDENT always
has the value "0xAC"
PLLCTL
Address: 0x05 (05)
Type: R/W
Software Reset: 0xA1
Hardware Reset: 0xA1
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
XTO_ XTOD OCLK SYS2O PPLD XTI2DS XTI2O UPD_F
BUF IS EN CLK IS PCLK CLK RAC
UPD_FRAC: when is set to 1, update FRAC in
the switching circuit. It is set to 1 after autoboot.
XTI2OCLK: when is set to 1, use the XTI as input
of the divider X instead of VCO output. It is set to
0 on HW reset.
XTI2DSPCLK: when is to 1, set use the XTI as in-
put of the divider S instead of VCO output. It is
set to 0 on HW reset.
PLLDIS: when set to 1, the VCO output is dis-
abled. It is set to 0 on HW reset.
SYS2OCLK: when is set to 1, the OCLK fre-
quency is equal to the system frequency. It is
useful for testing. It is set to 0 on HW reset.
OCLKEN: when is set to 1, the OCLK pad is en-
able as output pad. It is set to 1 on HW reset.
XTODIS: when is set to 1, the XTO pad is dis-
able. It is set to 0 on HW reset.
XTO_BUF: when this bit is set, the pin nr. 28
(OUT_CLOCK/DATA_REQ) is enabled. It is set
to 0 after autoboot.
PLLCTL (M)
Address: 0x06 (06)
Type: R/W
Software Reset: 0x0C
Hardware Reset: 0x0C
PLLCTL (N)
Address: 0x07 (07)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The M and N registers are used to configure the
STA014 PLL by DSP embedded software.
M and N registers are R/W type but they are
completely controlled, on STA014, by DSP soft-
ware.
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