SRK2001A Datasheet, PDF (16/20 Pages) STMicroelectronics – Auto-compensation of parasitic inductance

Operation description
SRK2001A
7.7
Layout guidelines
The GND pin is the return of the bias current of the device and return for gate drive currents:
it should be routed to the common point where the source terminals of both synchronous
rectifier MOSFETs are connected. When laying out the PCB, care must be taken in keeping
the source terminals of both SR MOSFETs as close to one another as possible and routing
the trace that goes to the GND separately from the load current return path. This trace
should be as short as possible and be as close to the physical source terminals as possible.
Doing the layout as more geometrically symmetrical as possible will help make the circuit
operation as much electrically symmetrical as possible.
Also drain-source voltage sensing should be done as physically close to the drain and
source terminals as possible in order to minimize the stray inductance involved by the load
current path that is in the drain-to-source voltage sensing circuit.
The usage of bypass capacitors between the V_CC and GND is recommended. They should
be the low-ESR, low-ESL type and located as close to the IC pins as possible. Sometimes,
a series resistor (in the tens ) between the converter's output voltage and the V_CC pin,
forming an RC filter along with the by-pass capacitor, is useful to get a cleaner V_CC voltage.
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