LNBH26L Datasheet, PDF (16/28 Pages) STMicroelectronics – Selectable output current limit by external resistor

I²C interface protocol
LNBH26L
7.2
Read mode transmission
In read mode the bytes sequence must be as follows:
● a START condition (S)
● a chip address byte with the LSb bit R/W=0
● the register address byte of the internal first register to be accessed
● a STOP condition (P)
● a new master transmission with the chip address byte and the LSb bit R/W=1
● after the acknowledge, the LNBH26L starts to send the addressed register content. As
long as the master keeps the acknowledge LOW, the LNBH26L transmits the next
address register byte content.
● the transmission is terminated when the master sets the acknowledge high with a
following stop bit.
Figure 11. Example of reading procedure starting with first status address 0X0 ^(b)
CHIP ADDRESS
REGISTER ADDRESS
CHIP ADDRESS
MSB
LSB
MSB
LSB
MSB
LSB
S 000100X
0 0 0 0 0XXX
P
S 000100X
STATUS 1
Add=0x0
STATUS 2
Add=0x1
MSB
LSB
MSB
LSB
DATA 1
Add=0x2
MSB
LSB
MSB
DATA 2
Add=0x3
LSB
MSB
DATA 3
Add=0x4
DATA 4
Add=0x5
LSB
MSB
LSB
P
A M10486v 1
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, read/write bit
X = 0/1, set the values to select the chip address (see Table 15 for pin selection) and to
select the register address (see Table 6 to Table 11).
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b. The reading procedure can start from any register address (Status 1, 2 or Data1..4) by simply setting the X
values in the register address byte (after the first chip address in the above figure). It can be also stopped from
the master by sending a STOP condition after any acknowledge bit.
Doc ID 022876 Rev 1