L6726A_10 Datasheet, PDF (16/35 Pages) STMicroelectronics – Single phase PWM controller

Application details
L6726A
depending on the output capacitor ESR. The DC gain of the modulator is simply the input
voltage V_IN divided by the peak-to-peak oscillator voltage ΔV_OSC.
V_OUT is scaled and transferred to FB node by the output resistor divider.
The compensation network closes the loop joining FB and COMP node with transfer
function ideally equal to -gm·Z_F.
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F_0dB) can be fixed choosing the right R_F; however, for stability, it
should not exceed F_SW/2π. To achieve a good phase margin, the control loop gain has to
cross 0 dB axis with -20 dB/decade slope.
As an example, Figure 9 shows an asymptotic bode plot of a type II compensation.
Figure 9. Example of type II compensation.
Gain
[dB]
OTA
open loop
F_Z
F_P
gain
closed loop
gain
compensation
gain
converter
open loop
gain
0dB
F_0dB
20log (gm·R_F)
20log [V_IN/ΔV_OSC·R_OS/(R_FB+R_OS)]
Log (Freq)
F_LC
F_ESR
● Open loop converter singularities:
a)
F_LC
=
----------------¹-----------------
2π L ⋅ C_OUT
b)
F_ESR
=
---------------------¹----------------------
2π ⋅ C_OUT ⋅ ESR
● Compensation Network singularities frequencies:
a)
F_Z
=
--------------¹----------------
2π ⋅ R_F ⋅ C_F
b)
F_P
=
------------------------¹-------------------------
2
π
⋅
R_F
⋅
⎛
⎝
-_CC----_F-^F---+-^â‹---^C-_C----^P-_P- _⎠⎞
16/35
Doc ID 12754 Rev 4