AN2009 Datasheet, PDF (16/39 Pages) STMicroelectronics – PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7MC

PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7MC
Figure 11. Oscilloscope waveforms: Current Mode
1. Current in Phase A
2. Signal on High Side
Switch of Phase A on
Triple Half Bridge
Configuration
3. Current Regulation
Signal through PWM
Compare U filtered
4. Current Feedback
Note: In speed regulation, the 12-bit timer PWM duty cycle only has to have the right value to
start the motor. Once the target speed is reached, the PWM duty cycle will be adjusted auto-
matically by the ST7MC.
4.2.2 PWM signal register setting in Current mode
In current mode, a combination of an internal clock and the output of the current comparator is
used to set the PWM signal, the registers described below are the ones used to set the fre-
quency and the minimum OFF time if needed from the PWM signal for the internal clock.
PRESCALER & SAMPLING REGISTER (MPRSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
SA3 SA2 SA1 SA0 X
X
X
X
Bits 7:4 = SA[3:0]: Sampling Ratio.
These bits contain the sampling ratio value for current mode. This sets the frequency of the
PWM according to the following table
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