STW81100 Datasheet, PDF (15/23 Pages) STMicroelectronics – MULTI-BAND RF FREQUENCY SYNTHESIZER WITH INTEGRATED VCOS

STW81100
8.1.4 STOP condition
A LOW to HIGH transition of the data bus SDA identifies start while the clock signal SCL is stable in the
HIGH state. A STOP condition terminates communications between the STW81100 and the Bus Master.
Figure 18.
SCL
SDA
START
STOP
8.1.5 Byte format and acknowledge
Every byte transferred on the SDA line must contain bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or
slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls
the SDA low to acknowledge the receipt of 8 bits data.
Figure 19.
SCL
1
2
3
7
8
9
//
SDA
START
MSB
//
ACKNOWLEDGMENT
FROM RECEIVER
8.1.6 Device addressing
To start the communication between the Master and the STW81100, the master must initiate with a start
condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device
select address and read or write mode.
The first 7 MSB‘s are the device address identifier, corresponding to the I²C-Bus definition. For the
STW81100 the address is set as “1100A₂A₁A₀”, 3bits programmable. The 8th bit (LSB) is the read or write
operation bit (RW; set to 1 in read mode and to 0 in write mode).
After a START condition the STW81100STW81100 identifies on the bus the device address and, if
matched, it will acknowledge the identification on SDA bus during the 9th clock pulse.
8.1.7 Single-byte write mode
Following a START condition the master sends a device select code with the RW bit set to 0. The
STW81100 gives an acknowledge and waits for the internal sub-address (1 byte). This byte provides ac-
cess to any of the internal registers.
After the reception of the internal byte sub-address the STW81100 again responds with an acknowledge.
A single byte write to sub-address 00H would affect DATA_OUT[119:112], so a single byte write with sub-
address 07H would affect DATA_OUT[63:56] and so on.
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