STA450A Datasheet, PDF (15/66 Pages) STMicroelectronics – XMRADIO SDARS SERVICE LAYER & SOURCE DECODER

STA450A
2.3 REGISTER MAP
The DSP HOST interface includes 256 registers.
HOST @
Name
Register
size
Mode
0x00 HOST_VERSION
8 bits
R
0x01 HOST_ID
8 bits
R
0x02 to Reserved
0x0F
0x10 HOST_SOFTRESET
8 bits
W
0x11 HOST_Plldata
8 bits
R–W
0x12 HOST_Pllpcm
0x13 HOST_cmd0
0x14 to Reserved
0x17
0x18 HOST_Pllcmd
3 bits
1 bit
R–W
R–W
8 bits
R–W
0x19 to Reserved
0x1B
0x1C HOST_I2cdiv
6 bits
R–W
0x1D HOST_Plladd
8 bits
R–W
0x1E HOST_SerialDivL
0x1F HOST_SerialDivH
0x20 to Reserved
0x2A
0x2B Host_Memory Access
0x2C to Reserved
0x39
0x3A Host_clkstop
0x3B to Reserved
0x3F
0x40 HOST_SOFTVER
0x41 HOST_EVENTINTE0
0x42 HOST_EVENTINTE1
0x43 HOST_EVENTINTE2
0x44 HOST_EVENTINTE3
0x45 HOST_EVENTINT0
0x46 HOST_EVENTINT1
8 bits
8 bits
R–W
R–W
4 bits
W
1bit
W
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
R–W
R–W
R–W
R–W
R–W
R–W
R–W
SW
Reset
0x10
0x20
NA
NC
NC
0
NC
0x0B
NC
0x00
0x00
0x00
NA
NA
NA
NA
NA
NA
NA
NA
HW
Reset
0x10
0x20
Comment
NA Soft reset of the DSP core and
peripherals
0 Data register to configure the
different configuration registers
01 PCM clock direction configuration
0 I2C Interrupt request
0 Command register to configure
the PLLs
0x0B
0
0x00
0x00
Hold time value of the data on
SDA versus SCL edges
Address register to configure the
different configuration registers
RS232 rate coeff L
RS232 rate coeff H
0x00 Enables core to access ucode
1 Stops the clock to the core
NA Software version (BCD)
NA EVENT Interrupt enable bit[7:0]
NA EVENT Interrupt enable bit[15:8]
NA EVENT Interrupt enable bit[23:16]
NA EVENT Interrupt enable bit[31:24]
NA EVENT Interrupt value bit[7:0]
NA EVENT Interrupt value bit[15:8]
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