M95256-DRE Datasheet, PDF (15/41 Pages) STMicroelectronics – 256-Kbit serial SPI bus EEPROM - 105 C Operation

M95256-DRE
4
Instructions
Instructions
Each command is composed of bytes (MSBit transmitted first), initiated with the instruction
byte, as summarized in Table 6.
If an invalid instruction is sent (one not contained in Table 6), the device automatically enters
a Wait state until deselected.
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
RDID
WRID
RDLS
LID
Table 6. Instruction set
Description
Write Enable
Write Disable
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
Read Identification Page
Write Identification Page
Reads the Identification Page lock status.
Locks the Identification page in read-only mode.
Instruction
format
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
1000 0011
1000 0010
1000 0011
1000 0010
For read and write commands to memory array and Identification Page, the address is
defined by two bytes as explained in Table 7.
Table 7. Significant bits within the two address bytes⁽¹⁾⁽²⁾
MSB Address byte
LSB Address byte
Instructions
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
READ or
WRITE
RDID or
WRID
RDLS or
LID
x A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0 A5 A4 A3 A2 A1 A0
0000010000000000
1. A: Significant address bit.
2. x: bit is Don’t Care.
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