M48T35AV_07 Datasheet, PDF (15/28 Pages) STMicroelectronics – 3.3V, 256Kbit (32Kbit x 8) TIMEKEEPER® SRAM

M48T35AV
Clock operations
Note:
binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be
modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration Byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –
2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M48T35AV may
require. The first involves simply setting the clock, letting it run for a month and comparing it
to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows
the designer to give the end user the ability to calibrate his clock as his environment may
require, even after the final product is packaged in a non-user serviceable enclosure.
The second approach is better suited to a manufacturing environment, and involves the use
of some test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit
in the Day Register is set to a '1,' and D7 of the Seconds Register is a '0' (Oscillator
Running), DQ0 will toggle at 512 Hz during a READ of the Seconds Register. Any deviation
from 512 Hz indicates the degree and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (WR001010) to be loaded into the Calibration Byte for
correction.
Setting or changing the Calibration Byte does not affect the Frequency Test output
frequency.
The FT Bit MUST be reset to '0' for normal clock operations to resume. The FT Bit is
automatically Reset on power-down.
For more information on calibration, see Application Note AN934, “TIMEKEEPER^®
Calibration.”
3.5
Note:
Century bit
Bit D5 and D4 of Clock Register 7FFCh contain the CENTURY ENABLE Bit (CEB) and the
CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
The WRITE Bit must be set in order to write to the CENTURY Bit.
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