M29F002T Datasheet, PDF (15/29 Pages) STMicroelectronics – 2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory

M29F002T, M29F002NT, M29F002B
Table 15. Write AC Characteristics, Write Enable Controlled
(T_A = 0 to 70°C or –40 to 85°C)
M29F002T / M29F002NT / M29F002B
Symbol Alt
Parameter
-70
-90
-120
V_CC = 5V ± 10% V_CC = 5V ± 10% V_CC = 5V ± 10% ^Unit
Standard
Interface
Standard
Interface
Standard
In terface
Min Max Min Max Min Max
t_AVAV
t_WC
Address Valid to Next Address
Valid
70
90
120
ns
t_ELWL
t_CS
Chip Enable Low to Write Enable
Low
0
0
0
ns
t_WLWH
t_WP
Write Enable Low to Write Enable
High
35
45
50
ns
t_DVWH
t_DS Input Valid to Write Enable High
30
45
50
ns
t_WHDX
t_DH
Write Enable High to Input
Transition
0
0
0
ns
t_WHEH
t_CH
Write Enable High to Chip Enable
High
0
0
0
ns
t_WHWL
t_WPH
Write Enable High to Write Enable
Low
20
20
20
ns
tAVWL
tAS Address Valid to Write Enable Low
5
5
5
ns
t_WLAX
t_AH
Write Enable Low to Address
Transition
45
45
50
ns
t_GHWL
Output Enable High to Write
Enable Low
0
0
0
ns
t_VCHEL
t_VCS V_CC High to Chip Enable Low
50
50
50
µs
t_WHGL
t_OEH
Write Enable High to Output
Enable Low
0
0
0
ns
t_PHPHH ^(1,2) t_VIDR RPNC Rise Time to V_ID
500
500
500
ns
t_PLPX
t_RP RPNC Pulse Width
500
500
500
ns
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
ChipErase (CE) Instruction. This instructionuses
six write cycles. The Erase Set-up command 80h
is written to address 555h on the third cycle after
the two Coded cycles. The Chip Erase Confirm
command 10h is similarly written on the sixth cycle
after another two Coded cycles. If the second
command given is not an erase confirm or if the
Coded cycles are wrong, the instruction aborts and
the device is reset to Read Array. It is not necessary
to program the array with 00h first as the P/E.C. will
automaticallydo this before erasing it to FFh. Read
operations after the sixth rising edge of W or E
output the Status Register bits. During the execu-
tionof theerase by the P/E.C.,Data Polling bit DQ7
returns ’0’, then ’1’ on completion. The Toggle bits
DQ2 and DQ6 toggle during erase operation and
stop when erase is completed. After completionthe
Status Register bit DQ5 returns’1’ if there has been
an Erase Failure.
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