L6996 Datasheet, PDF (15/26 Pages) STMicroelectronics – DINAMICALLY PROGRAMMABLE SYNCHRONOUS STEP DOWN CONTROLLER FOR MOBILE CPUs

L6996
in this case the maximum value is Q_MAXLS = 125nC.
The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This
prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect.
1.8 Digital to analog converter
The built-in digital to analog converter (DAC) allows the adjustment of the output voltage in correspondence to
the Table1 in pag 4: from 0.6V to 1V with 25mV steps, and from 1V to 1.75V with 50mV steps. The DAC can
receive the digital input from the CPU. The programmed voltage is available on VPROG pin, which is capable
of sourcing or sinking up to 250µA. The internal reference accuracy is ±1%.
1.9 Dynamically changing DAC code
L6996 detects as a transition any change in VID code which duration is larger than 200ns. Then, a timer forces
the chip in a 'transition state' for about 100µs. In such a state, output protections are disabled and OVP pin goes
high.
Current limit threshold can be reduced during the transition state duration by using an external mos shorting part
of the R_ILIM resistor. The MOSFET gate is driven by OVP. Reducing current limit threshold prevents from output
voltage overshoot/undershoot once the new-programmed voltage has been reached (see waveforms reported
below), especially when the droop is not implemented. Note that the reduced threshold must be however high
enough to allow the output capacitor to charge/discharge within the transition time. During the transition state
duration, zero-cross comparator is disabled and inductor current is allowed to reverse. A negative current limit
is introduced. During OFF time, if inductor current is negative and reaches the threshold, low side MOSFET is
forced OFF, and remain OFF, allowing negative current to flow across high side body diode, for at least T_ON.
After then, the low side or high side turns ON again, depending on PWM comparator output. This allows switch-
ing frequency to be close to steady state frequency also when the device works in negative current limit protec-
tion.
Dynamically changing the VID code is useful for portable computers, where the CPU is supply at a higher volt-
age when the AC-DC adapter is plugged-in, to increase speed. A lower voltage is instead provided when only
the battery powers the CPU, to save energy.
The dynamic transition is usually made at light load condition, to allow the full current to be available for charg-
ing/discharging the output capacitor:
Iout ~ 300mA
∆Vout_max ~250mV
The current limit threshold should be set high enough to charge/discharge the output capacitor within the tran-
sition state duration (see below). If the output voltage changing is higher than 250mV the system can detect an
overvoltage or undervoltage that can shut down the device.
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