L6917B Datasheet, PDF (15/33 Pages) STMicroelectronics – 5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER

L6917B
The power dissipated by the input capacitance is then equal to:
P_RMS = ESR ⋅ (I_RMS)²
Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the
high rms value needed by the CPU power supply application and also to minimize components cost, the input
capacitance is realized by more than one physical capacitor. The equivalent rms current is simply the sum of
the single capacitor's rms current.
Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible
to reduce switching noise above all during load transient. Ceramic capacitor can also introduce benefits in high
frequency noise decoupling, noise generated by parasitic components along power path.
Output Capacitor
Since the microprocessors require a current variation beyond 50A doing load transients, with a slope in the
range of tenth A/µs, the output capacitor is a basic component for the fast response of the power supply.
Dual phase topology reduces the amount of output capacitance needed because of faster load transient re-
sponse (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180°
phase shift between the two phases also reduces requirements on the output ESR to sustain a specified voltage
ripple.
When a load transient is applied to the converter's output, for first few microseconds the current to the load is
supplied by the output capacitors. The controller recognizes immediately the load transient and increases the
duty cycle, but the current slope is limited by the inductor value.
The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):
∆V_OUT = ∆I_OUT · ESR
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
∆V_OUT = ₂-----_â‹---_C-----_O----_U----_T----_â‹---₍---_V----_I^∆--_N--^I--_MO2----^UI--_N--^T---_â‹-^â‹--_D-^L---_M-----_A---_X-----–-----_V----_O----_U----_T---₎-
Where D_MAX is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load
transient and the lower is the output voltage static ripple.
Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current ∆IL between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
L = -^V----^I-^N-_f--_s--–---_â‹--^V_∆----_I^O--_L--^U----^T-- ⋅ ^V---_V--^O---_I-^UN----^T-
Where f_SW is the switching frequency, V_IN is the input voltage and V_OUT is the output voltage.
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. The response time is the time required by the inductor to change its current
from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by
the output capacitors. Minimizing the response time can minimize the output capacitance required.
The response time to a load transient is different for the application or the removal of the load: if during the ap-
plication of the load the inductor is charged by a voltage equal to the difference between the input and the output
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