L6206Q Datasheet, PDF (15/27 Pages) STMicroelectronics – DMOS dual full bridge driver

L6206Q
5
Application information
Application information
A typical application using the L6206Q device is shown in Figure 14. Typical component
values for the application are shown in Table 7. A high quality ceramic capacitor in the range
of 100 to 200 nF should be placed between the power pins (VS_A and VS_B) and ground near
the L6206Q to improve the high frequency filtering on the power supply and reduce high
frequency transients generated by the switching. The capacitors connected from the
EN_A/OCD_A and EN_B/OCD_B nodes to ground set the shutdown time for bridge A and bridge
B respectively when an overcurrent is detected (see Section 4.3: Non-dissipative
overcurrent detection and protection). The two current sources (SENSE_A and SENSE_B)
should be connected to power ground with a trace length as short as possible in the layout.
To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or
GND (low logic level) (see Table 3.).
It is recommended to keep power ground and signal ground separated on the PCB.
Table 7. Component values for typical application
Component
Value
C₁
C₂
C_BOOT
C_P
C_ENA
C_ENB
C_REF
D₁
D₂
R_CLA
R_CLB
R_ENA
R_ENB
R_P
100 F
100 nF
220 nF
10 nF
5.6 nF
5.6 nF
68 nF
1N4148
1N4148
5 k
5 k
100 k
100 k
100 
DocID022028 Rev 3
15/27
27