AN3316 Datasheet, PDF (15/42 Pages) STMicroelectronics – SPC560B power and mode management

AN3316
Device modes
Peripherals management
Each peripheral clock source can be switched on or off independently when it is not used, to
optimize power consumption. The ME module manages the clock gating of each peripheral,
defining peripherals state (active/frozen) in each mode as following:
● 8 Running registers (ME_RUN_PC[0..7]) to generate 8 different configuration in
running modes
● 8 Low-Power registers (ME_LP_PC[0..7]) to generate 8 different configuration in low
power modes
● One register for each peripheral (ME_PCTL[x]) that address one of the Running
configuration and one of the Low-Power configuration
Following is an example that describes how to clock gate/enable EMIOS peripheral:
Mode Entry - example
EMIOS0 Clock Gating
● Configure EMIOS in the following way
– Active in DRUN, RUN0, STOP mode
– Clock Gated in the others mode
Steps
● Configuration of Running mode
– ME_RUN_PC[1].DRUN = 1
– ME_RUN_PC[1].RUN0 = 1
● Configuration of Low Power mode
– ME_LP_PC[2].STOP = 1
● Configuraion of EMIOS (peripheral number = 72)
– ME_PTCL[72].RUN_CFG = 1
– ME_PTCL[72].LP_CFG = 2
Figure 7. Peripheral configuration example
DRUN
RUN0
EMIOS active
STOP
Doc ID 18232 Rev 2
15/42