AN2381 Datasheet, PDF(15/47 Page) STMicroelectronics – low voltage linear accelerometer

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AN2381 Datasheet, PDF (15/47 Pages) STMicroelectronics – low voltage linear accelerometer

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AN2381

Digital interfaces

4.1.3

I2C Read and Write sequences

The previous subsequences are used to realize actual write and read sequences described

in the tables below.

Transfer when Master is writing one byte to slave:

Master

SA + W

SUB

DATA

Slave

SAK

Transfer when Master is writing multiple bytes to slave:

Master ST SA + W

SUB

DATA

Slave

SAK

Transfer when Master is receiving (reading) one byte of data from slave:

Master ST SA + W

Slave

SAK

SUB

SAK

SR SA + R

NMAK SP

SAK DATA

Transfer when Master is receiving (reading) multiple bytes of data from slave:

Master

Slave

ST SA + W

SAK

SUB

SAK

SR SA + R

MAK

SAK DATA

Master

MAK

NMAK

Slave

DATA

Data are transmitted in byte format. Each data transfer contains 8 bits. The number of bytes

transferred per transfer is unlimited. Data is transferred with the Most Significant Bit (MSB)

first. If a receiver canât receive another complete byte of data until it has performed some

other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state.

Data transfer only continues when the receiver is ready for another byte and releases the

data line. If a slave receiver doesnât acknowledge the slave address (i.e. it is not able to

receive because it is performing some real time function) the data line must be left HIGH by

the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line

while the SCL line is HIGH is defined as a STOP condition (SP). Each data transfer must be

terminated by the generation of a STOP condition.

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