ST92196A Datasheet, PDF (141/268 Pages) STMicroelectronics – 8/16-BIT MCU FOR TV APPLICATIONS WITH UP TO 96K ROM, ON-SCREEN-DISPLAY AND 1 OR 2 DATA SLICERS

- ON SCREEN DISPLAY CONTROLLER (OSD)
OSD CONTROLLER (Cont’d)
8.5.8 Programming the Row Buffers
The 2 row buffers are based on the same structure
(Figure 59):
– Next Buffer Start Address
– Row Mode
– Horizontal Shift
– Row Character Count
8.5.8.1 Next Buffer Start Address And Row Mode
Address in Segment 22h: 2p (Bits 15:8), 2p + 1 (Bits 7:0). See Figure 59.
15
87
0
WM2 WM1
NSA8 NSA7 NSA6 NSA5 NSA4 NSA3 NSA2 NSA1 0
To display more than 1 character row on the
screen, you must specify the start address of the
next OSDRAM row buffer (the row buffer contain-
ing the next row to be displayed when the current
row is completely processed). Two bytes are re-
served for this in the OSDRAM. (See Figure 59).
As it is possible to display each row using different
modes (serial, basic parallel, and extended paral-
lel), the row mode has to be specified for the cur-
rent row buffer.
Bits 15:14 = WM[2:1] Serial/parallel Row Mode
control
These bits define the row mode for the buffer de-
fined by the Next Buffer Start Address (NSA[8:0]
bits). Refer to Table 25 for details.
Bits 13:9 = Free for the user
Bits 8:0 = NSA[8:0] Next buffer Start Address
These bits define the start address of the next row
buffer.
As row buffer start addresses are always even ad-
dresses, the NSA0 is not implemented, and Bit 0 is
forced to 0 by hardware.
Table 25. Serial/Parallel mode control
WM2
1
1
0
0
WM1
1
0
1
0
Mode
(reserved)
Extended Parallel
Basic Parallel
Serial
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