XRA00 Datasheet, PDF (14/40 Pages) STMicroelectronics – UHF, EPCglobal, Contactless Memory IC 96 bit ePC with Inventory and Kill Function

XRA00
Figure 19. Transmission of XRA00 Answers
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XRA00 Answer Bit Cell Variation. Durind the
Reader Request Frame command, the XRA00
synchronizes its internal PLL (Phase Lock Loop)
to the Master Clock Time Period, t₀, generated by
Figure 20. XRA00 Answer Bit Cell Variation
the Reader. Due to the internal PLL drift in the
XRA00, the answer data bit cell period t_tagbitcell
may vary by up to ±1/8t₀.
Nominal Symbol at Start of Reply
−1/8t0
ttagbitcell
+1/8t0
Fast (−1/8t0) Symbol
Slow (+1/8t0) Symbol
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Table 4. XRA00 Backscattered Answer Modulation Parameters
Symbol
Description
Master Clock Time Period for a single bit sent to the XRA00
North American Operation
t₀
Master Clock Time Period for a single bit sent to the XRA00
European Operation Preliminary Data
t_tagbitcell
XRA00 to Reader data bit cell period
t_{tagbitcellTol}
XRA00 to Reader data bit cell period Tolerance
(measured on 96+16+8 bits)
2 / t₀
Answer Frame Data Rate (2/t₀) for North American Operation
Answer Frame Data Rate (2/t₀) for European Operation
Preliminary Data
Min
Max Units
12.5
16.6
µs
40
66.67
1/2 x t₀
±1/8 x t₀
120
160
30
50
µs
µs
µs
kbps
kbps
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