VIPER100B Datasheet, PDF (14/20 Pages) STMicroelectronics – SMPS PRIMARY I.C.

VIPER100B/BSP
used. It mixes a high performance compensation
network together with a separate high value soft
start capacitor. Both soft start time and regulation
loop bandwidth can be adjusted separately.
If the device is intentionally shut down by putting
the COMP pin to ground, the device is also
performing start-up cycles, and the V_DD voltage is
oscillating between VDDon and VDDoff. This voltage
can be used for supplying external functions,
provided that their consumption doesn’t exceed
0.5mA. Figure 17 shows a typical application of
this function, with a latched shut down. Once the
”Shutdown” signal has been activated, the device
remains in the off state until the input voltage is
removed.
TRANSCONDUCTANCE ERROR AMPLIFIER
The VIPer100B/BSP includes a transconductance
error amplifier. Transconductance Gm is the
change in output current (I_COMP) versus change
in input voltage (VDD). Thus:
G_m
=
∂ I_COMP
∂ VDD
The output impedance ZCOMP at the output of this
amplifier (COMP pin) can be defined as:
Z_COMP
=
∂ V_COMP
∂ I_COMP
=
1
G_m
x
∂ V_COMP
∂ V_DD
This last equation shows that the open loop gain
A_VOL can be related to G_m and Z_COMP:
AVOL = Gm x ZCOMP
where Gm value for VIPer100B/BSP is 1.5 mA/V
typically.
Gm is well defined by specification, but ZCOMP
and therefore AVOL are subject to large
tolerances. An impedance Z can be connected
between the COMP pin and ground in order to
define more accurately the transfer function F of
the error amplifier, according to the following
equation, very similar to the one above:
F(S) = Gm x Z(S)
The error amplifier frequency response is
reported in figure 10 for different values of a
simple resistance connected on the COMP pin.
The unloaded transconductance error amplifier
shows an internal Z_COMP of about 330 KΩ. More
complex impedance can be connected on the
COMP pin to achieve different compensation
laws. A capacitor will provide an integrator
function, thus eliminating the DC static error, and
a resistance in series leads to a flat gain at higher
frequency, insuring a correct phase margin. This
configuration is illustrated on figure 18.
As shown in figure 18 an additional noise filtering
capacitor of 2.2 nF is generally needed to avoid
any high frequency interference.
It can be also interesting to implement a slope
compensation when working in continuous mode
with duty cycle higher than 50%. Figure 19 shows
such a configuration. Note that R1 and C2 build
the classical compensation network, and Q1 is
injecting the slope compensation with the correct
polarity from the oscillator sawtooth.
EXTERNAL CLOCK SYNCHRONIZATION:
The OSC pin provides a synchronisation
capability, when connected to an external
Figure 16: Mixed Soft Start and Compensation
Figure 17: Latched Shut Down
D2
VIPer100B
VDD
-
OSC
13V +
DRAIN
COMP SOURCE
D1
D3
R3
+ C3
C4
R1
C1
R2
+ C2
AUXILIARY
WINDING
Shutdown
Q2
R3
R1
V IPer100B
VDD
-
OSC
13V +
R2
DRAIN
COMP SOURCE
R4
Q1
D1
FC0 0131B
F C0 0 1 10 B
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