STV1601A Datasheet, PDF (14/17 Pages) STMicroelectronics – SERIAL INTERFACE TRANSMISSION ENCODER

STV1601A
Figure 19 : Relation between NRZ and NRZI Signals
Time scale
NRZ signal
NRZI signal
NRZ to NRZI conversion
NRZI signal
NRZI inverted signal
NRZ to NRZI conversion
Figure 20 : VCO Temperature Compensation and Free Running Adjustment
STV1601A
TN1
TRP
FV
PCK
35
34
33
36
10µF
C1
22kΩ
L1
Small signal
transistor
Frequency monitor
1kΩ
10kΩ
V _EE
Jitter trap
Since the internally generated serial clock is locked
to the incoming parallel clock, there exists periodic
jitter components which are generated from the
phase comparison process of the PLL.
A serial resonant circuit (trap) connected between
TRP (Pin 34) and VEE tuned at the parallel clock
frequency reduces effectively the fundamental
component of the jitter well below the specification
(±0.25ns).
Recommended values of C1 and L1 are given in
the following table.
RECOMMENDED VALUES OF THE TRAP CIRCUIT
COMPONENT
C1 (pF)
L1 (µH)
STANDARD
D2
D1
PAL
NTSC
150
240
300
0.2
0.3
0.4
An important remark in a practical implementation
is that TRP node is an input of a very sensitive
voltage-frequency converter (VCO) which can be
easily disturbed by any pick-up noise.
Hence, the trap circuit should be carefully located
and be kept as short as possible from the Pin 34 in
order to avoid noise problems.
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