STM32F373CCT6 Datasheet, PDF (14/131 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, up to 256KB Flash+32KB SRAM timers, 4 ADCs (12/16-bit), 3 DACs, 2 comp., 2.0-3.6 V operation

Functional overview
STM32F37xxx
3.7
3.7.1
3.7.2
3.7.3
Power management
Power supply schemes
• V_DD: external power supply for I/Os and the internal regulator. It is provided externally
through V_DD pins, and can be 2.0 to 3.6 V.
• V_DDA = 2.0 to 3.6 V:
– external analog power supplies for Reset blocks, RCs and PLL
– supply voltage for 12-bit ADC, DACs and comparators (minimum voltage to be
applied to V_DDA is 2.4 V when the 12-bit ADC and DAC are used).
• V_DDSD12 and V_DDSD3 = 2.2 to 3.6 V: supply voltages for SDADC1/2 and SDADCD3
sigma delta ADCs. Independent from V_DD/V_DDA.
• V_BAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers when V_DD is not present.
Power supply supervisor
• The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry.
It is always active, and ensures proper operation starting from/down to 2 V. The device
remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the
need for an external reset circuit. The POR monitors only the V_DD supply voltage.
During the startup phase it is required that V_DDA should arrive first and be greater than
or equal to V_DD.
• The PDR monitors both the V_DD and V_DDA supply voltages, however the V_DDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V_DDA is higher than or
equal to V_DD.
The device features an embedded programmable voltage detector (PVD) that monitors the
V_DD power supply and compares it to the VPVD threshold. An interrupt can be generated
when V_DD drops below the V_PVD threshold and/or when V_DD is higher than the V_PVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR), and power-down.
• The MR mode is used in the nominal regulation mode (Run)
• The LPR mode is used in Stop mode.
• The power-down mode is used in Standby mode: the regulator output is in high
impedance, and the kernel circuitry is powered down thus inducing zero consumption.
The voltage regulator is always enabled after reset. It is disabled in Standby mode.
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DocID022691 Rev 4