STM32F102CBT6 Datasheet, PDF (14/80 Pages) STMicroelectronics – Medium-density USB access line, ARM-based 32b MCU with 64/128KB Flash, USB FS, 6 timers, ADC & 8 com. interfaces

Description
STM32F102x8, STM32F102xB
Boot modes
At startup, boot pins are used to select one of five boot options:
• Boot from User Flash
• Boot from System Memory
• Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
• V_DD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through V_DD pins.
• V_SSA, V_DDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
and PLL (minimum voltage to be applied to V_DDA is 2.4 V when the ADC is used).
V_DDA and V_SSA must be connected to V_DD and V_SS, respectively.
• V_BAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V_DD is not present.
For more details on how to connect power pins, refer to Figure 8: Power supply scheme.
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V_DD is below a specified threshold, V_POR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V_DD/V_DDA power supply and compares it to the V_PVD threshold. An interrupt can be
generated when V_DD/V_DDA drops below the V_PVD threshold and/or when V_DD/V_DDA is
higher than the V_PVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 11: Embedded reset and power control block characteristics for the values of
V_POR/PDR and V_PVD.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
• MR is used in the nominal regulation mode (Run)
• LPR is used in the Stop mode
• Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
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DocID15056 Rev 5