ST7538 Datasheet, PDF (14/30 Pages) STMicroelectronics – POWER LINE FSK TRANSCEIVER

ST7538
3.6 Receiving Mode
The receive section is active when RxTx Pin =”1” and REG_DATA=0.
The input signal is read on RAI Pin using SGND as ground reference and then pre-filtered by a Band pass
Filter (62kHz max. bandwidth at -3dB). The Pre-Filter can be removed setting one bit in the Control Reg-
ister. The Input Stage features a wide dynamic range to receive Signal with a Very Low Signal to Noise
Ratio. The Amplitude of the applied waveform is automatically adapted by an Automatic Gain Control
block (AGC) and then filtered by a Narrow Band Band-Pass Filter centered around the Selected Channel
Frequency (14kHz max. bandwidth at -3dB). The resulting signal is down-converted by a mixer using a
sinewave generated by the FSK Modulator. Finally an Intermediate Frequency Band Pass-Filter (IF Filter)
improves the Signal to Noise ration before sending the signal to the FSK demodulator. The FSK demod-
ulator then send the signal to the RX Logic for final digital filtering. Digital filtering Removes Noise spikes
far from the BAUD rate frequency and Reduces the Signal Jitter. RxD Line is forced at logic level “0” when
neither mark or space frequencies are detected on RAI Pin.
Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have a correct de-
modulation.
While ST7538 is in Receiving Mode (RxTx pin =”1”), the transmit circuitry, Power Line Interface included,
are turned off. This allows the device to achieve a very low current consumption (5 mA typ). In Receiving
mode ATOP2 pin is internally connected to PAVSS.
) ^{■ High Sensitivity Mode}
t(s ^{It is possible to increase ST7538 Receiving Sensitivity setting to “1” the High Sensitivity Bit of Control}
Register. This Function allows to increase the communication reliability when the ST7538 sensitivity is
uc ^{the limiting factor.}
d _{■ Synchronization Recovery System (PLL)}
ro ST7538 embeds a Clock Recovery System to feature a Synchronous data exchange with the Host
P _Controller.
te ^{The clock recovery system is realized by means of a second order PLL. Data on the data line (RxD) are}
le ^{stable on CLR/T line rising edge (CLR/T Falling edge synchronized to RxD line transitions ± LOCK-IN}
Range).
so _{The PLL Lock-in and Lock-out Range is ±π/2. When the PLL is in the unlock condition, CLR/T and RxD}
b _{lines are forced to a low logic level.}
O _{When PLL is in unlock condition it is sensitive to RxD Rising and Falling Edges. The maximum number}
- _{of transition required to reach the lock-in condition is 5. When in lock-in condition the PLL is sensitive}
t(s) ^{only to RxD rising Edges to reduce the CLR/T Jitter.}
ST7538 PLL is forced in the un-lock condition, when more than 32 equal symbols are received.
c _{Due to the fact that the PLL, in lock-in condition, is sensitive only to RxD rising edge, sequences equal}
du ^{or longer than 15 equal symbols can put the PLL into the un-lock condition.}
ro _{Figure 11. ST7538 PLL lock-in range}
lete ^P _CLR/T
Obso _RxD
LOCK-IN RANGE
D03IN1417
14/30