M24C64T-FCU Datasheet, PDF (14/36 Pages) STMicroelectronics – 64-Kbit serial IC bus EEPROM 4 balls CSP

Instructions
5
Instructions
M24C64T-FCU
5.1
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 5, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Table 3. Most significant address byte
A15
A14
A13
A12
A11
A10
A9
A8
Table 4. Least significant address byte
A7
A6
A5
A4
A3
A2
A1
A0
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10^th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle t_W is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (t_W), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
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