AN2847 Datasheet, PDF (14/31 Pages) STMicroelectronics – This document provides application information for the low-voltage 3-axis digital output

Operating modes
AN2847
Note:
Table 8. CTRL_REG5 - sleep to wake configuration
TurnOn1
TurnOn0
Sleep to wake status
0
0
Sleep to wake function disabled
0
1
An interrupt event has occurred and the system is generating data at
ODR
1
0
Not allowed
1
1
Sleep to wake function enabled
Table 9 and Table 10 show the typical power consumption values for the different operating
modes.
Higher data rates correspond to lower device resolution.
Table 9. Power consumption - normal mode (µA)
ODR
50 Hz
100 Hz
Power consumption
250
255
400 Hz
290
1000 Hz
370
Table 10. Power consumption - low power mode (µA)
ODR\ODR_LP
0.5 Hz
1 Hz
2 Hz
50 Hz
10
20
30
100 Hz
10
15
20
400 Hz
10
15
20
1000 Hz
5
10
15
5 Hz
60
40
40
30
10 Hz
99
80
80
60
3.1
Normal mode
In Normal mode, data are generated at the data rate (ODR) selected through the DR bits
and for the axis enabled through the Zen, Yen and Xen bits of the CTRL_REG1 register.
Data generated for a disabled axis is 00h.
Data interrupt generation is active and configured through the INT1_CFG and INT2_CFG
registers.
3.2
Power down mode
When the device is in Power Down mode, almost all internal blocks of the device are
switched off to minimize power consumption. Digital interfaces (I²C and SPI) are still active
to allow communication with the device. The content of the configuration register is
preserved and output data registers are not updated, thus keeping in memory the last data
sampled before going to Power Down mode.
Typical turn-on time to return to Normal mode is 1 ms + 1/ODR.
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