AN2798 Datasheet, PDF (14/38 Pages) STMicroelectronics – Complete DDR2/3 memory power supply

Configuration
Figure 10. JP1 (DDRSEL) setting
AN2798
1.8 V output voltage
(default position)
1.5 V output voltage
1.5 V output voltage
JP1 options when JP3 is in the lower position
Forced PWM
(default position)
Non Audible Pulse-Skip
Pulse-Skip
JP1 options when JP3 is in the upper position
5.3
JP2 output discharge (DSCG pin)
The JP2 jumper is used to select the desired output discharge when both S3 and S5 signals
are tied low. In the upper position the outputs are not discharged at all, while in the lower
position the outputs are independently discharged using the internal MOSFETs (22 Ω for
VDDQ and VTT, 1.5 kΩ for VTTREF).
The tracking discharge is programmed by putting JP2 in the central position. This discharge
mode relies on the connection of the LDOIN pin to the VDDQ output, see Section 6: Test
setup on page 16 for details. If an external rail is used to supply the LDO, the tracking
discharge cannot be used because the device can be damaged while attempting to sink 1 A
from the LDO input.
Figure 11. JP2 (DSCG) setting
No Discharge
(default position)
Tracking Discharge
Non-Tracking Discharge
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