AN2353 Datasheet, PDF (14/18 Pages) STMicroelectronics – Designing an application with the ST10F27x devices

Analog Digital Converter (ADC)
AN2353
when increasing or decreasing the input voltage from Varef/2 (hold capacitor is precharged
to Varef/2 before sampling to reduce charge/discharge time).
Refer to the product data sheet for details.
6.3
Errors due to high frequencies from input signal
Small but high frequency signal variations can result in increased conversion error: During
sampling time, the analog signal is fed to an internal auto-zero circuitry. Signal variations (at
least two opposite transitions) during this time can generate auto-zero error. Signal
variations during sampling time generate excessively high or low conversion results; big
variations (Example: 150mV peak to peak variations at 1.5 MHz, with a 2.5V offset for 1µs
sampling time) can generates clamped results (0x000 or 0x3FFh).
Although the sample and hold internal circuitry is integrating signal variations, other internal
analog circuitry can be affected by signal transitions during sampling time.
The input analog signal should always be low pass filtered to ensure that high frequencies
are rejected.
6.4
Reducing ADC errors
There are four possible optimizations:
● Minimize the total source impedance seen by the ST10
This means choosing sensors with low output impedance (not always easy for some
types of sensor) and minimizing the serial resistance of any protection devices between
the analog source and the input pin (while still providing a voltage protection level
compatible with the circuit specification).
● Match the sample time to the analog source impedance
● Match the sample time to the analog filter cut-off frequency to remove high frequencies
The ST10F27x sampling time (ADC silicon configuration) shall be should be / must be /
is 5 to 10 times shorter than the period of the cut-off frequency of the low-pass filter on
ADC input signal.
● Reduce noise at the input pin
Add an external RC filter (with attention to the source internal resistance). Compute the
average value of different samples in the software routine.
6.5
Varef power-up and power-down sequence
Varef should always be lower than the 5V supply (maximum = V_DD + 0.1V). This is
especially true for the power-up and power-down sequence when external devices are used
to generate Varef.
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