STM32W108HB Datasheet, PDF (134/179 Pages) STMicroelectronics – High-performance, IEEE 802.15.4 wireless system-on-chip

Analog-to-digital converter
STM32W108CB, STM32W108HB
Table 17. Typical ADC input configurations (continued)
ADC P input
ADC N input
ADC_MUXP
ADC_MUXN
VREF
VREF/2
10
9
VDD_PADSA/2
VREF/2
11
9
Purpose
Calibration
Calibration
Input range
ADC inputs can be routed through input buffers to expand the input voltage range. The input
buffers have a fixed 0.25 gain and the converted data is scaled by that factor.
With the input buffers disabled the single-ended input range is 0 to VREF and the differential
input range is -VREF to +VREF. With the input buffers enabled the single-ended range is 0
to VDD_PADS and the differential range is -VDD_PADS to +VDD_PADS.
The input buffers are enabled for the ADC P and N inputs by setting the ADC_HVSELP and
ADC_HVSELN bits respectively, in the ADC_CFG register. The ADC accuracy is reduced
when the input buffer is selected.
Sample time
ADC sample time is programmed by selecting the sampling clock and the clocks per
sample.
● The sampling clock may be either 1 MHz or 6 MHz. If the ADC_1MHZCLK bit in the
ADC_CFG register is clear, the 6 MHz clock is used; if it is set, the 1 MHz clock is
selected. The 6 MHz sample clock offers faster conversion times but the ADC
resolution is lower than that achieved with the 1 MHz clock.
● The number of clocks per sample is determined by the ADC_PERIOD bits in the
ADC_CFG register. ADC_PERIOD values select from 32 to 4096 sampling clocks in
powers of two. Longer sample times produce more significant bits. Regardless of the
sample time, converted samples are always 16-bits in size with the significant bits left-
aligned within the value.
Table 18 shows the options for ADC sample times and the significant bits in the conversion
results.
Table 18. ADC sample times
ADC_PERIOD
Sample
Clocks
Sample Time (µs)
1 MHz clock 6 MHz clock
Sample Frequency (kHz)
1 MHz clock 6 MHz clock
0
32
32
5.33
31.3
188
1
64
64
10.7
15.6
93.8
2
128
128
21.3
7.81
46.9
3
256
256
42.7
3.91
23.4
4
512
512
85.3
1.95
11.7
5
1024
1024
170
0.977
5.86
6
2048
2048
341
0.488
2.93
7
4096
4096
682
0.244
1.47
Significant
Bits
5
6
7
8
9
10
11
12
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Doc ID 16252 Rev 2