ST92141 Datasheet, PDF (131/179 Pages) STMicroelectronics – 8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL

ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont’d))
PERIPHERAL CONTROL REGISTER 2 (PCR2)
R250 - Read/Write
Register Page: 48
Reset Value: 0000 0000 (00h)
7
0
POLARITY SELECTION REGISTER (PSR)
R251 - Read/Write
Register Page: 48
Reset Value: 0000 0000 (00h)
7
0
GPIE RSE CWSE CVSE CUSE C0SE SDT DTS
NMIL UDIS PUH PUL PVH PVL PWH PWL
Bit 7 = GPIE: Global Peripheral Interrupt Enable.
0: Disable all IMC controller interrupts.
1: Enable all IMC controller interrupts.
Bit 7 = NMIL: Non Maskable Interrupt Level.
0: Low level of NMI event is acknowledged.
1: High level of NMI event is acknowledged.
Bit 6 = RSE: Enable Software Data Transfer to
Repetition register.
0: Disable loading of Repetition register by SDT bit
1: Enable loading of Repetition register by SDT bit
Bit 5 = CWSE: Enable Software Data Transfer to
Compare W.
0: Disable load of Compare W register by SDT bit
1: Enable load of Compare W register by SDT bit
Bit 4 = CVSE: Enable Software Data Transfer to
Compare V register.
0: Disable loading of Compare V register by SDT
bit
1: Enable loading of Compare V register by SDT
bit
Bit 3 = CUSE: Enable Software Data Transfer to
Compare U register.
0: Disable loading of Compare U register by SDT
bit
1: Enable loading of Compare U register by SDT
bit
Bit 2 = C0SE: Enable Software Data Transfer to
Compare 0 register.
0: Disable loading of Compare 0 register by SDT
bit
1: Enable loading of Compare 0 register by SDT
bit
Bit 1 = SDT: Software Data Transfer
0: No effect
1: Transfer Data from preload to compare register
(while DTS=1) (This bit is reset by hardware).
Bit 0 = DTS: Data Transfer Mode Selection.
0: Hardware transfer using Repetition counter
1: Software transfer using SDT bit.
Bit 6 = UDIS: Up-Down Interrupt Select.
When the PWM Counter is working in Zerocen-
tered Mode the meaning is:
0: The Compare interrupts (CPU, CPV, CPW) are
issued when the Counter is counting up.
1: The Compare interrupts (CPU, CPV, CPW) are
issued when the Counter is counting down.
This bit has no effect when the Counter is working
in Classical Mode
Bit 5 = PUH: Polarity of Uh phase.
0: Positive logical level.
1: Complemented logical level.
Bit 4 = PUL: Polarity of Ul phase.
0: Positive logical level.
1: Complemented logical level.
Bit 3 = PVH: Polarity of Vh phase.
0: Positive logical level.
1: Complemented logical level.
Bit 2 = PVL: Polarity of Vl phase.
0: Positive logical level.
1: Complemented logical level.
Bit 1 = PWH: Polarity of Wh phase.
0: Positive logical level.
1: Complemented logical level.
Bit 0: PWL: Polarity of Wl phase.
0: Positive logical level.
1: Complemented logical level.
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