TDA7705_10 Datasheet, PDF (13/42 Pages) STMicroelectronics – Highly integrated tuner for AM/FM car radio

TDA7705
Function description
Table 3. Boot mode pin configuration
Configuration:
I²C (addr. 0 x C2)
I²C (addr. 0 x C8)
SPI
Pin
at reset operation at reset operation at reset operation
39
RDSINT
37
SCL
36
SDA
35
(SPI_MISO)
34
(SPI_CS)
0
RDS interrupt
0
RDS interrupt
1
RDS interrupt
in
out
in
out
in
out
I²C SCL
I²C SCL
SPI CLK
x
x
x
in
in
in
I²C SDA
I²C SDA
SPI MOSI
x
x
x
in/out
in/out
in
0
1
1
SPI MISO
-
-
in
in
in
out
SPI SS
x
-
x
-
x
in
If I²C serial bus is chosen as means of communication with the controlling device, two chip
addresses are possible: 0xC2/C3 or 0xC8/C9, depending on the initial configuration of pins
35 and 39.
The status of pins 35 and 39 during the reset phase can be set to:
high, through external <10 kΩ resistors tied to 3.3V (pin 32), or
low, by not forcing any voltage on them from outside, as 50 kohm internal pull-down
resistors are present on said pins.
To make sure the boot mode is correctly latched up at start-up, it is advisable to keep the
RSTN line low until the IC supply pins have reached their steady state, and then for an
additional time T_reset (see Section 3.4.8).
2.13.2
I²C bus protocol
I²C requires two signals: clock (SCL) and data (SDA - bidirectional). The protocol requires
an acknowledge after any 8-bit transmission.
A "write" communication example is shown in the figure below, for an unspecified number of
data bytes (see the relevant technical documentation for frame structure description):
Figure 3. I²C "write" sequence
SDA
SCL
a7
a6
…
a0
START
clk1
clk2
…
address
clk8
clk9
ACK
d7
clk1
d6
…
clk2
…
data
d0
clk8
clk9
ACK
STOP
Doc ID 15938 Rev 8
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