TDA7566 Datasheet, PDF (13/19 Pages) STMicroelectronics – MULTIFUNCTION QUAD POWER AMPLIFIER WITH BUILT-IN DIAGNOSTICS FEATURES

TDA7566
I²C BUS INTERFACE
Data transmission from microprocessor to the TDA7566 and viceversa takes place through the 2 wires I²C BUS inter-
face, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
Data Validity
As shown by fig. 20, the data on the SDA line must be stable during the high period of the clock.
The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and Stop Conditions
As shown by fig. 21 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 22).
The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDAline is stable LOW during this clock pulse.
* Transmitter
master (µP) when it writes an address to the TDA7566
slave (TDA7566) when the µP reads a data byte from TDA7566
** Receiver
slave (TDA7566) when the µP writes an address to the TDA7566
master (µP) when it reads a data byte from TDA7566
Figure 20. Data Validity on the I²C BUS
SDA
Figure 21.
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 22.
SCL
SDA
START
D99AU1032
I²CBUS
STOP
SCL
1
2
3
7
8
9
SDA
START
MSB
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
13/19