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| STM32F101ZGT6 Datasheet, PDF (13/108 Pages) STMicroelectronics – XL-density access line, ARM-based 32-bit MCU with 768 KB to 1 MB Flash, 15 timers, 1 ADC and 10 communication interfaces | |||
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STM32F101xF, STM32F101xG
Description
Figure 2. Clock tree
/3#?/54
/3#?).
/3#?).
/3#?/54
-#/
-(Z
(3) 2#
(3)
0,,32# 0,,-5,
X
X X X
0,,
37
(3)
0,,#,+
(3%
393#,+ !("
-(Z
MAX
0RESCALER
-(Z
(3% /3#
0,,8402%
#33
,3% /3#
K(Z
,3%
TO 24#
24##,+
24#3%,;=
&,)4&#,+
TO &LASH PROGRAMMING
INTERFACE
0ERIPHERAL CLOCK
ENABLE
-(Z MAX
#LOCK
%NABLE
&3-##,+ TO &3-#
(#,+
TO !(" BUS CORE
MEMORY AND $-!
TO #ORTEX 3YSTEM TIMER
!0"
0RESCALER
&#,+ #ORTEX
FREE RUNNING CLOCK
-(Z MAX
0#,+
TO !0"
0ERIPHERAL #LOCK PERIPHERALS
%NABLE
4)-
)F !0" PRESCALER X
ELSE X
TO 4)-
AND
4)-X#,+
0ERIPHERAL #LOCK
%NABLE
!0"
0RESCALER
-(Z MAX
0#,+
TO !0" PERIPHERALS
0ERIPHERAL #LOCK
%NABLE
4)-
)F !0" PRESCALER X
ELSE X
TO 4)- 4)-
AND 4)-
4)-X#,+
0ERIPHERAL #LOCK
%NABLE
!$#
0RESCALER
TO !$#
!$##,+
,3) 2#
K(Z
,3)
TO INDEPENDENT WATCHDOG )7$'
)7$'#,+
-AIN
#LOCK /UTPUT
-#/
0,,#,+
(3)
(3%
393#,+
,EGEND
(3% (IGH SPEED EXTERNAL CLOCK SIGNAL
(3) (IGH SPEED INTERNAL CLOCK SIGNAL
,3) ,OW SPEED INTERNAL CLOCK SIGNAL
,3% ,OW SPEED EXTERNAL CLOCK SIGNAL
AI
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.
Doc ID 17143 Rev 2
13/108
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