M95M02-A125 Datasheet, PDF (13/39 Pages) STMicroelectronics – Automotive 2 Mbit serial SPI bus EEPROM

M95M02-A125
Operating features
Status Register bits
BP1
BP0
0
0
0
1
1
0
1
1
Table 3. Write-protected block size
Protected block
Protected array addresses
None
Upper quarter
Upper half
Whole memory
None
3000h - 3FFFFh
2000h - 3FFFFh
0000h - 3FFFFh plus Identification page
SRWD bit and W input signal
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect pin (W) signal. When the SRWD bit is written to 0, it is possible to write the Status
Register, regardless of whether the pin Write Protect (W) is driven high or low.
When the SRWD bit is written to 1, two cases have to be considered, depending on the
state of the W input pin:
• Case 1: if pin W is driven high, it is possible to write the Status Register.
• Case 2: if pin W is driven low, it is not possible to write the Status Register (WRSR is
discarded) and therefore SRWD,BP1,BP0 bits cannot be changed (the size of the
protected memory block defined by BP1,BP0 bits is frozen).
Case 2 can be entered in either sequence:
• Writing SRWD bit to 1 after driving pin W low, or
• Driving pin W low after writing SRWD bit to 1.
The only way to exit Case 2 is to pull pin W high.
Note: if pin W is permanently tied high, the Status Register cannot be write-protected.
The protection features of the device are summarized in Table 4.
SRWD bit
0
1
1
Table 4. Protection modes
W signal
Status
X
Status Register is writable.
1
0
Status Register is write-protected.
3.5
Identification page
The M95M02-A125 offers an Identification page (256 byte) in addition to the 2 Mbit memory.
The Identification page contains two fields:
• Device identification: the three first byte are programmed by STMicroelectronics with
the Device identification code, as shown in Table 5.
• Application parameters: the bytes after the Device identification code are available for
application specific data.
DocID026881 Rev 5
13/39
38