M24M01-R Datasheet, PDF (13/30 Pages) STMicroelectronics – 1 Mbit serial I²C bus EEPROM

M24M01-R
Device operation
3.5
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 2-bit Chip Enable
“Address” (E2, E1). To address the memory array, the 4-bit device type identifier is 1010b.
Up to four memory devices can be connected on a single I²C bus. Each one is given a
unique 2-bit code on the Chip Enable (E1, E2) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E1, E2) inputs.
The 8^th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9^th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 5. Operating modes
Mode
RW bit WC⁽¹⁾ Bytes
Initial sequence
Current Address Read
1
0
Random Address Read
1
Sequential Read
1
Byte Write
0
Page Write
0
1. X = V_IH or V_IL.
X
1 Start, device select, RW = 1
X
Start, device select, RW = 0, Address
1
X
reStart, device select, RW = 1
X
≥ 1 Similar to Current or Random Address Read
V_IL
1 Start, device select, RW = 0
V_IL
≤256 Start, device select, RW = 0
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