M24128-BFMC6TG Datasheet, PDF (13/40 Pages) STMicroelectronics – 128-Kbit serial I²C bus EEPROM

M24128-BW M24128-BR M24128-BF M24128-DF
Device operation
4.5
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
Table 2. Device select code
Device type identifier⁽¹⁾
Chip Enable address⁽²⁾ RW
b7
b6
b5
b4
b3
b2
b1
b0
Device select code
when addressing the
1
0
1
0
E2
E1
E0
RW
memory array
Device select code
when accessing the
Identification page
1
0
1
1
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared with the value read on input pins E0, E1,and E2.
When the device select code is received, the device only responds if the Chip Enable
Address is the same as the value on the Chip Enable (E2, E1, E0) inputs.
The 8^th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9^th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
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