AN4661 Datasheet, PDF (13/33 Pages) STMicroelectronics – This application note is intended for system designers

AN4661
Power supplies
1.3.6
Figure 5. Reset circuit
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Regulator OFF mode
This feature is available only on packages featuring the BYPASS_REG pin.
• The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode
allows supplying externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
• Since the internal voltage scaling is not managed internally, the external voltage value
must be aligned with the targeted maximum frequency. The two 2.2 μF ceramic
capacitors should be replaced by two 100 nF decoupling capacitors.
• When the regulator is OFF, there is no more internal monitoring on V12. An external
power supply supervisor should be used to monitor the V12 of the logic power domain.
PA0 pin should be used for this purpose, and act as power-on reset on V12 power
domain.
In regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows resetting a part of the V12 logic
power domain which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
• The over-drive and under-drive modes are not available.
• The Standby mode is not available.
Note:
The following conditions must be respected:
• VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
• If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the
time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until
VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V.
• Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally.
• If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V,
then a reset must be asserted on PA0 pin.
The minimum value of V12 depends on the maximum frequency targeted in the application.
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