ST10F269-T3 Datasheet, PDF (129/160 Pages) STMicroelectronics – 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM

ST10F269-T3
xxIC (yyyyh / zzh)
15 14 13 12 11 10
-
-
-
-
-
-
SFR Area
9
8
7
6
5
-
- xxIR xxIE
RW RW
4
3
ILVL
RW
Reset Value: --00h
2
1
0
GLVL
RW
Bit
GLVL
ILVL
xxIE
xxIR
Function
Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
XPERCON (F024h / 12h)
ESFR
Reset Value: --05h
15 14 13 12 11 10 9 8 7 6 5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
- RTCEN XRAM2EN XRAM1EN CAN2EN CAN1EN
RW
RW
RW
RW
RW
CAN1EN
CAN2EN
XRAM1EN
XRAM2EN
RTCEN
CAN1 Enable Bit
‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins can be
used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if
CAN2EN is also ‘0’.
‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2 Enable Bit
‘0’: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled. P4.4 and P4.7 pins can be
used as general purpose I/Os. Address range 00’EE00h-00’EEFFh is only directed to external memory if
CAN1EN is also ‘0’.
‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAM1 Enable Bit
‘0’: Accesses to external memory within space 00’E000h to 00’E7FFh. The 2K Bytes of internal XRAM1
are disabled.
’1’: Accesses to the internal 2K Bytes of XRAM1.
XRAM2 Enable Bit
‘0’: Accesses to the external memory within space 00’C000h to 00’DFFFh. The 8K Bytes of internal
XRAM2 are disabled.
’1’: Accesses to the internal 8K Bytes of XRAM2.
RTC Enable Bit
’0’: Accesses to the on-chip Real Time Clock are disabled, external access performed. Address range
00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and CAN2EN are ’0’ also
’1’: The on-chip Real Time Clock is enabled and can be accessed.
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