SPC564A74B4 Datasheet, PDF (128/157 Pages) STMicroelectronics – Up to 4 multiply and accumulate operations per cycle

Electrical characteristics
SPC564A74L7, SPC564A80B4, SPC564A80L7
Table 48. DSPI timing^(1),(2) (continued)
#
Symbol C
Characteristic
Condition
Min.
Max. Unit
Data Setup Time for Inputs
D
Master (MTFE = 0)
D
9
t_SUI CC ^{D Slave}
D
Master (MTFE = 1, CPHA =
0)⁽¹²⁾
V_DDEH=4.5–5.5 V
V_DDEH=3–3.6 V
20
23.5
2
8
—
—
—
ns
—
D
V_DDEH=4.5–5.5 V
20
—
Master (MTFE = 1, CPHA = 1)
D
V_DDEH=3–3.6 V
23.5
—
Data Hold Time for Inputs
D Master (MTFE = 0)
-4
—
10
t_HI
CC ^{D Slave}
D
Master (MTFE = 1,
CPHA = 0)⁽¹²⁾
7
—
ns
21
—
D Master (MTFE = 1, CPHA = 1)
-4
—
Data Valid (after SCK edge)
D
Master (MTFE = 0)
D
V_DDEH=4.5–5.5 V
—
V_DDEH=3–3.6 V
—
D
11 t_SUO CC
Slave
D
V_DDEH=4.5–5.5 V
—
V_DDEH=3–3.6 V
—
D Master (MTFE = 1, CPHA = 0)
—
5
6.3
25
27
ns
21
D
V_DDEH=4.5–5.5 V
—
5
Master (MTFE = 1, CPHA = 1)
D
V_DDEH=3–3.6 V
—
6.3
Data Hold Time for Outputs
D
Master (MTFE = 0)
D
V_DDEH=4.5–5.5 V
V_DDEH=3 –3.6 V
–5
–7.5
12 t_HO CC D Slave
5.5
D Master (MTFE = 1, CPHA = 0)
3
—
—
—
ns
—
D
V_DDEH=4.5–5.5 V
–5
—
Master (MTFE = 1, CPHA = 1)
D
V_DDEH=3–3.6 V
–7.5
—
1. All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on medium-speed pads. DSPI signals using slow
pads have an additional delay based on the slew rate. DSPI timing is specified at V_DDEH = 3 to 3.6 V and V_DDEH =
4.5 to 5.5 V, T_A = T_L to T_H, and C_L = 50 pF with SRC = 0b11.
2. Data is verified at f_SYS = 102 MHz and 153 MHz (100 MHz and 150 MHz + 2% frequency modulation).
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Doc ID 15399 Rev 9