STM32F446MC Datasheet, PDF (125/201 Pages) STMicroelectronics – 8- to 14-bit parallel camera interface up to 54 Mbytes

STM32F446xC/E
Electrical characteristics
open-drain. When configured as open-drain, the PMOS connected between the I/O pin and
V_DD is disabled, but is still present.
The I²C characteristics are described in Table 61. Refer also to Section 6.3.17: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Symbol
Table 61. I²C characteristics
Parameter
Standard mode
I²C⁽¹⁾⁽²⁾
Fast mode I²C⁽¹⁾⁽²⁾
Unit
Min
Max
Min
Max
t_w(SCLL) SCL clock low time
t_w(SCLH) SCL clock high time
t_su(SDA) SDA setup time
t_h(SDA) SDA data hold time
t_{v(SDA, ACK)} Data, ACK valid time
t_r(SDA)
t_r(SCL)
SDA and SCL rise time
t_f(SDA)
t_f(SCL)
SDA and SCL fall time
t_h(STA) Start condition hold time
t_su(STA)
Repeated Start condition
setup time
4.7
-
1.3
4.0
-
0.6
250
-
100
-
3450⁽³⁾
-
-
3.45
-
-
1000
-
-
300
-
4.0
-
0.6
4.7
-
0.6
-
µs
-
-
900⁽⁴⁾
0.9
ns
300
300
-
µs
-
t_su(STO) Stop condition setup time
4.0
-
0.6
-
μs
t_w(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
μs
Pulse width of the spikes
t_SP
that are suppressed by the
analog filter for standard and
-
fast mode
-
0.05
0.09⁽⁵⁾
μs
C_b
Capacitive load for each bus
line
-
400
-
400
pF
1. Guaranteed based on test during characterization.
2.
fa_{PcChLieK1vemfuasstt}
bmeodateleI₂aCstfr2eqMuHenzctioesa,cahniedvae
standard mode I²C frequencies. It must
multiple of 10 MHz to reach the 400 kHz
bmeaaxitmleuamstI₂4CMfaHszt
to
mode
clock.
3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
5. The minimum width of the spikes filtered by the analog filter is above t_SP(max).
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