STA381BWTR Datasheet, PDF (125/174 Pages) STMicroelectronics – Sound Terminal® 2.1-channel high-efficiency digital audio system

STA381BW
Register description: Sound Terminal compatibility
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled). This
register also controls the EAPD/FFX4B output pin when OCFG = 10.
7.7
7.7.1
Volume control registers (addr 0x06 - 0x0A)
Mute/line output configuration register
D7
LOC1
0
D6
LOC0
0
D5
Reserved
0
D4
BQBALL
0
D3
C3M
0
D2
C2M
0
D1
C1M
0
LOC[1:0]
Table 131. Line output configuration
Line output configuration
00
Line output fixed - no volume, no EQ
01
Line output variable - CH3 volume effects line output, no EQ
10
Line output variable with EQ - CH3 volume effects line output
11
Reserved
D0
MMUTE
0
Line output is only active when OCFG = 00. In this case LOC determines the line output
configuration. The source of the line output is always channel 1 and 2 inputs.
Bit R/W RST
4
R/W
0
Bit R/W RST
3
R/W
0
2
R/W
0
Name
BQBALL
Description
Global biquad bypass
0: Biquad filters active
1: All the biquad filters are bypassed (pass-through)
Table 132. Mute configuration
Name
Description
C3M
Channel 3 mute
0 - No mute condition. It is possible to set the channel
volume
1 - Channel 3 in hardware mute
C2M
Channel 2 mute
0 - No mute condition. It is possible to set the channel
volume
1 - Channel 2 in hardware mute
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