ST72321B Datasheet, PDF (125/187 Pages) STMicroelectronics – 64/44-pin 8-bit MCU with 32 to 60K Flash/ROM, ADC, five timers, SPI, SCI, I2C interface

I²C BUS INTERFACE (Cont’d)
I²C CLOCK CONTROL REGISTER (CCR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0
Bit 7 = FM/SM Fast/Standard I²C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
0: Standard I²C mode
1: Fast I²C mode
Bit 6:0 = CC[6:0] 7-bit clock divider.
These bits select the speed
pending on the I²C mode.
of the bus (F_SCL) de-
They are not cleared
when the interface is disabled (PE=0).
Refer to the Electrical Characteristics section for
the table of values.
Note: The programmed F_SCL assumes no load on
SCL and SDA lines.
I²C DATA REGISTER (DR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7:0 = D[7:0] 8-bit Data Register.
These bits contain the byte to be received or trans-
mitted on the bus.
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the following data bytes are received one
by one after reading the DR register.
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