ST7LITE49M Datasheet, PDF (123/188 Pages) STMicroelectronics – 8-bit MCU with single voltage Flash memory data EEPROM, ADC, 8/12-bit timers, and I²C interface

ST7LITE49M
On-chip peripherals
Bit 3 = BTF Byte Transfer Finished bit
This bit is set by hardware as soon as a byte is correctly received or transmitted with
interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by
a read or write of DR register. It is also cleared by hardware when the interface is
disabled (PE=0).
– Following a byte transmission, this bit is set after reception of the acknowledge
clock pulse. In case an address byte is sent, this bit is set only after the EV6 event
(See Figure 57). BTF is cleared by reading SR1 register followed by writing the
next byte in DR register.
– Following a byte reception, this bit is set after transmission of the acknowledge
clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading
the byte from DR register.
The SCL line is held low while BTF=1.
0: byte transfer not done
1: byte transfer succeeded
Bit 2 = ADSL Address matched bit (slave mode). This bit is set by hardware as soon as the
received slave address matched with the OAR register content or a general call is
recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register
or by hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 1 = M/SL Master/Slave bit
This bit is set by hardware as soon as the interface is in Master mode (writing
START=1). It is cleared by hardware after detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
Bit 0 = SB Start bit (master mode).
This bit is set by hardware as soon as the Start condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1
register followed by writing the address byte in DR register. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
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