ST7LITE1XB Datasheet, PDF (120/157 Pages) STMicroelectronics – 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

ST7LITE1xB
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
13.4.1 Supply Current
T_A = -40 to +85°C unless otherwise specified
Symbol
Parameter
Conditions
Typ Max Unit
Supply current in RUN mode
Supply current in WAIT mode
Supply current in SLOW mode
I_{DD Supply current in SLOW WAIT mode7}
Supply current in HALT mode⁵⁾
Supply current in AWUFH mode ⁶⁾⁷⁾
f_CPU=8MHz ¹⁾
f_CPU=8MHz ²⁾
f_CPU=250kHz ³⁾
f_CPU=250kHz ⁴⁾
-40°C≤T_A≤+125°C
-40°C≤T_A≤+125°C
7
9
3
3.6
mA
0.7
0.9
0.5
0.8
<1
6
µA
20
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at V_DD or V_SS (no load), all peripherals
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at V_DD or V_SS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
3. SLOW mode selected with f_CPU based on f_OSC divided by 32. All I/O pins in input mode with a static value at V_DD or
V_SS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with f_CPU based on f_OSC divided by 32. All I/O pins in input mode with a static value at
V_DD or V_SS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
5. All I/O pins in output mode with a static value at V_SS (no load), LVD disabled. Data based on characterization results,
tested in production at V_DD max and f_CPU max.
6. All I/O pins in input mode with a static value at V_DD or V_SS (no load). Data tested in production at V_DD max. and f_CPU
max.
7. This consumption refers to the Halt period only and not the associated run period which is software dependent.
Figure 71. Typical I_DD in RUN vs. f_CPU
9
.5
8
1
7
2
4
6
6
8
5
4
3
2
1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Vdd (V)
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
Figure 72. Typical I_DD in RUN at f_CPU = 8MHz
9
8
7
6
140°C
5
90°C
4
25°C
3
-5°C
2
-45°C
1
0
Note2: Grap2h.5display3s data 3b.5eyond t4he norm4.5al opera5 ting ra5n.5ge of 3V6 - 5.5V6.5
Vdd (V)
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
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