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| ST7DALI Datasheet, PDF (120/141 Pages) STMicroelectronics – 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI | |||
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ST7DALI
CONTROL PIN CHARACTERISTICS (Contâd)
Figure 86. RESET pin protection when LVD is enabled.1)2)3)4)5)
VDD
ST72XXX
EXTERNAL
RESET
0.01µF
Recommended
RON
Filter
PULSE
GENERATOR
INTERNAL
RESET
WATCHDOG
LVD RESET
Figure 87. RESET pin protection when LVD is disabled.1)2)3)
Recommended
VDD
VDD
VDD
ST72XXX
USER
EXTERNAL
RESET
CIRCUIT
Required
0.01µF
4.7kâ¦
0.01µF
RON
Filter
PULSE
GENERATOR
INTERNAL
RESET
WATCHDOG
1. The reset network protects the device against parasitic resets.
2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the VIL max. level specified in section 13.9.1 on page 119. Otherwise the reset will not be taken into account internally.
4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for IINJ(RESET) in section 13.2.2 on page 101.
5. When the LVD is enabled, it is mandatory not to to connect a pull-up resistor and a capacitor to VDD on the RESET pin.
120/141
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