VIPER20A-E Datasheet, PDF (12/34 Pages) STMicroelectronics – SMPS primary I.C.

Operation description
VIPer20A-E
As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase
above the 13V regulation level, forcing the output voltage of the transconductance amplifier to
low state (V_COMP < V_COMPth). This situation leads to the shutdown mode where the power
switch is maintained in the Off state, resulting in missing cycles and zero duty cycle. As soon as
V_DD gets back to the regulation level and the V_COMPth threshold is reached, the device operates
again. The above cycle repeats indefinitely, providing a burst mode of which the effective duty
cycle is much lower than the minimum one when in normal operation. The equivalent switching
frequency is also lower than the normal one, leading to a reduced consumption on the input
main supply lines. This mode of operation allows the VIPer20A-E to meet the new German
"Blue Angel" Norm with less than 1W total power consumption for the system when working in
stand-by mode. The output voltage remains regulated around the normal level, with a low
frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because
of the output capacitors and low output current drawn in such conditions.The normal operation
resumes automatically when the power gets back to higher levels than P_STBY.
5.3 High voltage start-up current suorce
An integrated high voltage current source provides a bias current from the DRAIN pin during
the start-up phase. This current is partially absorbed by internal control circuits which are
placed into a standby mode with reduced consumption and also provided to the external
capacitor connected to the V_DD pin. As soon as the voltage on this pin reaches the high voltage
threshold V_DDon of the UVLO logic, the device becomes active mode and starts switching. The
start-up current generator is switched off, and the converter should normally provide the
needed current on the V_DD pin through the auxiliary winding of the transformer, as shown on
(see Figure 11).
In case there are abnormal conditions where the auxiliary winding is unable to provide the low
voltage supply current to the V_DD pin (i.e. short circuit on the output of the converter), the
external capacitor discharges to the low threshold voltage V_DDoff of the UVLO logic, and the
device goes back to the inactive state where the internal circuits are in standby mode and the
start-up current source is activated. The converter enters a endless start-up cycle, with a start-
up duty cycle defined by the ratio of charging current towards discharging when the VIPer20-E
tries to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle
while the power dissipation at start-up is approximately 0.6W, for a 230Vrms input voltage.
This low value start-up duty cycle prevents the application of stress to the output rectifiers as
well as the transformer when a short circuit occurs.
The external capacitor C_VDD on the V_DD pin must be sized according to the time needed by the
converter to start up, when the device starts switching. This time t_SS depends on many
parameters, among which transformer design, output capacitors, soft start feature, and
compensation network implemented on the COMP pin. The following formula can be used for
defining the minimum capacitor needed:
where:
C_V
DD
>
---^I--^D----^D---^t--^S---^S---
V_DDhyst
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I_DD is the consumption current on the V_DD pin when switching. Refer to specified I_DD1 and I_DD2
values.
t_SS is the start up time of the converter when the device begins to switch. Worst case is
generally at full load.
V_DDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).