M41T93_08 Datasheet, PDF (12/51 Pages) STMicroelectronics – Serial SPI bus RTC with battery switchover

Operation
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Operation
M41T93
The M41T93 clock operates as a slave device on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI bus-compatible. The bus signals are SCL,
SDI, and SDO (see Table 1 on page 7 and Figure 5 on page 10). The device is selected
when the chip enable input (E) is held low. All instructions, addresses and data are shifted
serially in and out of the chip. The most significant bit is presented first, with the data input
(SDI) sampled on the first rising edge of the clock (SCL) after the chip enable (E) goes low.
The 32 bytes contained in the device can then be accessed sequentially in the following
order:
1 Tenths/hundredths of a second register
2 Seconds register
3 Minutes register
4 Century/hours register
5 Day register
6 Date register
7 Month register
8 Year register
9 Digital calibration register
10 Watchdog register
11-15 Alarm1 registers
16 Flags register
17 Timer value register
18 Timer control register
19 Analog calibration register
20 Square wave register
21-25 Alarm2 registers
26-32 User RAM
The M41T93 clock continually monitors V_CC for an out-of tolerance condition. Should V_CC
fall below V_RST, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system.
The power input will also be switched from the V_CC pin to the external battery when V_CC falls
below the battery back-up switchover voltage (V_SO = V_RST). At this time the clock registers
will be maintained by the battery supply. As system power returns and V_CC rises above V_SO,
the battery is disconnected, and the power supply is switched to external V_CC.
Write protection continues until V_CC reaches V_PFD (min) plus t_REC (min). For more
information on battery storage life refer to application note AN1012.
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