M24C32-DRE Datasheet, PDF (12/41 Pages) STMicroelectronics – 32-Kbit serial IC bus EEPROM - 105C operation

Device operation
M24C32-DRE
3.5
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, as
shown in Table 2 .
The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable
address (E2, E1, E0). A device select code handling any value other than 1010b (to select
the memory) or 1011b (to select the Identification page) is not acknowledged by the memory
device.
Up to eight memory devices can be connected on a single I²C bus. Each one is given a
unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select code is
received, the memory device only responds if the Chip Enable Address is the same as the
value decoded on the E2, E1, E0 inputs.
The 8^th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
Table 2. Device select code
Device type identifier⁽¹⁾
Chip Enable address⁽²⁾ RW
b7
b6
b5
b4
b3
b2
b1
b0
When accessing the
memory
1
0
1
0
E2
E1
E0
RW
When accessing the
Identification page
1
0
1
1
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 bits are compared with the value read on input pins E0,E1,E2.
If a match occurs on the device select code, the corresponding memory device gives an
acknowledgment on Serial Data (SDA) during the 9^th bit time. If the memory device does not
match the device select code, it deselects itself from the bus, and goes into Standby mode.
Once the memory device has acknowledged the device select code (Table 2), the memory
device waits for the master to send two address bytes (most significant address byte sent
first, followed by the least significant address byte (Table 3). The memory device responds
to each address byte with an acknowledge bit.
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