L5991AD13TR Datasheet, PDF (12/23 Pages) STMicroelectronics – PRIMARY CONTROLLER WITH STANDBY

L5991 - L5991A
in fig.28) holds the pin low in order to ensure that
the external MOS cannot be turned on acciden-
tally. The peculiarity of this circuit is its ability to
mantain the same sink capability (typically, 20mA
@ 1V) from VCC = 0V up to the start-up threshold.
When the threshold is exceeded and the L5991
starts operating, VREFOK is pulled high (refer to fig.
28) and the circuit is disabled.
It is then possible to omit the "bleeder" resistor
(connected between the gate and the source of
the MOS) ordinarily used to prevent undesired
switching-on of the external MOS because of
some leakage current.
Figure 28. Pull-Down of the output in UVLO.
V_REFOK
OUT
10
12
SGND
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Pin 11. PGND (Power Ground). The current loop
during the discharge of the gate of the external
MOS is closed through this pin. This loop should
be as short as possible to reduce EMI and run
separately from signal currents return.
Pin 12. SGND (Signal Ground). This ground refer-
ences the control circuitry of the IC, so all the
ground connections of the external parts related
to control functions must lead to this pin. In laying
out the PCB, care must be taken in preventing
switched high currents from flowing through the
SGND path.
Figure 29. Internal LEB.
Pin 13. ISEN (Current Sense). This pin is to be
connected to the "hot" lead of the current sense
resistor Rsense (being the other one grounded), to
get a voltage ramp which is an image of the cur-
rent of the switch (IQ). When this voltage is equal
to:
V_13pk
=
I_Qpk ⋅
R_sense
=
VCOMP
3
−
1.4
(9)
the conduction of the switch is terminated.
To increase the noise immunity, a "Leading Edge
Blanking" of about 100ns is internally realized as
shown in fig. 29. Because of that, the smoothing
RC filter between this pin and Rsense could be re-
moved or, at least, considerably reduced.
Pin 14. DIS (Device Disable). When the voltage
on pin 14 rises above 2.5V the IC is shut down
and it is necessary to pull VCC (IC supply voltage,
pin 8) below the UVLO threshold to allow the de-
vice to restart.
The pin can be driven by an external logic signal
in case of power management, as shown in fig.
30. It is also possible to realize an overvoltage
protection, as shown in the section " Application
Ideas".If used, bypass this pin to ground with a fil-
ter capacitor to avoid spurious activation due to
noise spikes. If not, it must be connected to
SGND.
Pin 15. DC-LIM (Maximum Duty Cycle Limit). The
upper extreme, Dx, of the duty cycle range de-
pends on the voltage applied to this pin. Approxi-
mately,
D_x
≅
R_T
R_T
+ 230
(10)
if DC-LIM is grounded or left floating. Instead,
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I
13
ISEN
1.2V
2V
3V
+
0
-
CLK
FROM E/A
PWM
+ ^COMPARATOR
-
+
-
OVERCURRENT
COMPARATOR
TO PWM
LOGIC
TO FAULT
LOGIC
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