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STM32L151XX Datasheet, PDF (118/121 Pages) STMicroelectronics – Ultra-low-power 32-bit MCU ARM-based Cortex-M3, 128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC
Revision history
STM32L151x6/8/B, STM32L152x6/8/B
Table 70. Document revision history (continued)
Date
Revision
Changes
25-Feb-2011
4
cont’d
Updated Table 23: Typical and maximum current consumptions in
Standby mode on page 61 (IDD (WU from Standby) instead of (IDD (WU
from Stop).
Table 24: Typical and maximum timings in Low power modes on
page 62: updated condition for Wakeup from Stop mode, regulator in
Run mode; updated max values for Wakeup from Stop mode, regulator
in low power mode; updated max values for tWUSTDBY.
Table 25: Peripheral current consumption on page 63: updated values
for column Low power sleep and run; updated Flash values; renamed
ADC1 to ADC; updated IDD (LCD) value; updated units; added values for
IDD (RTC) and IDD (IWDG); updated footnote 1 and 3; added foot note 2
concerning ADC.
Table 26: High-speed external user clock characteristics on page 65:
added min value for tw(HSE)/tw(HSE) OSC_IN high or low time; added
max value for tr(HSE)/tf(HSE) OSC_IN rise or fall time; updated IL for typ
and max values.
Table 27: Low-speed external user clock characteristics on page 66:
updated max value for IL.
Table 28: HSE 1-24 MHz oscillator characteristics on page 68:
renamed i2 as IHSE and updated max value; updated max values for
IDD(HSE).
Table 29: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 69:
updated max value for ILSE.
Table 30: HSI oscillator characteristics on page 71: updated some min
and max values for ACCHSI.
Table 32: MSI oscillator characteristics on page 72: updated parameter,
typ, and max values for DVOLT(MSI).
Table 35: Flash memory and data EEPROM characteristics on
page 74: updated typ values for tprog.
Table 44: I/O AC characteristics on page 81: updated some max values
for 01, 10, and 11; updated min value; updated footnotes.
Table 55: ADC accuracy on page 92: updated typ values and some of
the test conditions for ENOB, SINAD, SNR, and THD.
Table 57: DAC characteristics on page 96: updated footnote 7 and
added footnote 8.
Updated leakage value in Figure 26: Typical connection diagram using
the ADC.
Added Figure 27: Maximum dynamic current consumption on VREF+
supply pin during ADC conversion.
Added Table 56: RAIN max for fADC = 16 MHz on page 94
Figure 28: Power supply and reference decoupling (VREF+ not
connected to VDDA): replaced all 10 nF capacitors with 100 nF
capacitors.
Figure 29: Power supply and reference decoupling (VREF+ connected to
VDDA): replaced 10 nF capacitor with 100 nF capacitor.
118/121
Doc ID 17659 Rev 8